Field
This disclosure relates generally to memories, and more specifically, to sensing states of memory cells within a memory.
Related Art
Memory arrays are characterized by an array of memory cells, addressed in one direction by row (word line) decoding and in the other direction by column (bit line) decoding. The state of the memory cell in the read mode is sensed by applying a read voltage/current to a selected bit line and enabling a selected word line which selects a unique memory cell. The impedance difference of the memory cell relative to a reference memory cell (or a complementary memory cell written to the opposite state) is then sensed either using current sensing or voltage sensing techniques. Non-volatile memories (NVMs) are usually configured in large array blocks, leading to long bit lines. The consequence of long bit lines and dense layout leads to significant bit line metal resistance so that the metal resistance during sensing varies depending on which word line is selected. Also, with scaling, the variation of the bit line resistance increases (due, for example, to line roughness, CD variation, local and global variations) to a point where the conductance of the memory cell is of the same order as the bit line metal resistance. This becomes a problem when trying to sense the memory cell state without error. Therefore, there is a need for a sensing method which provides an improved read operation even in the presence of parasitic resistance.